1. Technical Field
The invention concerns a complementary bipolar semiconductor device, hereinafter also referred to as a CBi semiconductor device, comprising                a substrate of a first conductivity type,        active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged,        vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions,        vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions,        collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and        shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions.        
The invention further concerns a process for the production of such a complementary bipolar semiconductor device.
2. Discussion of Related Art
For reasons relating to circuitry engineering it is often advantageous to have complementary bipolar transistors and complementary metal oxide semiconductor (CMOS) transistors at the same time on a monolithic semiconductor chip. A technology which aims at the production of precisely that transistor range is referred to as complementary bipolar CMOS technology or CBiCMOS technology or process, while the combined production of only one type of bipolar transistor, usually an npn bipolar transistor, jointly with CMOS transistors, is referred to as BiCMOS technology or BiCMOS process.
Usually, bipolar transistors are used in CBiCMOS or BiCMOS chips, hereinafter also referred to as hybrid chips, in circuitry parts where their high-frequency efficiency which is better in many respects in comparison with CMOS transistors is useful. The CMOS transistors are often used in hybrid chips, as in pure CMOS chips, primarily in circuitry blocks which serve for digital signal processing.
Due to that typical allocation of tasks as between bipolar and CMOS transistors hybrid chips generally include incomparably more CMOS transistors (typically several millions) than bipolar transistors (typically some thousand to tens of thousands). Particularly because of that “unbalance”, the usual practice in the development of BiCMOS and CBiCMOS technologies is to take as the basic starting point an existing basic CMOS process in which the technological steps for production of the bipolar components are subsequently integrated. In that respect in the ideal situation that integration process should involve the following features:    a) modular bipolar integration: so-called CMOS libraries, small “elementary circuits” of the basic CMOS process which can be effectively used for designing complex digital circuit blocks must also operate in the derived BiCMOS or CBiCMOS process. That requires bipolar integration not to alter the CMOS transistor properties in comparison with the basic process beyond a tolerable, generally extremely slight degree.    b) inexpensive bipolar integration: integration of the bipolar components should be effected in a way which adds as few additional process steps as possible, in particular also lithographic steps, to the basic CMOS process.    c) high-efficiency bipolar integration: bipolar transistors are to be available in a number of variants, generally characterized by various combinations of collector-emitter breakdown voltage, measured with open base terminal (BVCEO) and maximum transit frequency (fT), in the BiCMOS or CBiCMOS process and in that respect should as far as possible have high-frequency properties which come very close to those which could be implemented in the best-case scenario in pure bipolar technology, that is to say in particular also without having regard to a) and b).
It is easy to imagine that reconciling to some extent feature c) with features a) and b) represents a very great challenge in the development of BiCMOS but in particular CBiCMOS technologies.
The high-frequency efficiency of silicon-based bipolar transistors (referred to as bipolar junction transistors or BJT) has been substantially improved in recent years by the use of a hetero-base layer produced by means of epitaxy. In that case the hetero-base layer comprises a mixture of silicon and germanium (SiGe), wherein the Ge component is often varied deliberately within the layer along its direction of growth. Transistors with such a base layer are referred to as SiGe-HBTs (or heterojunction bipolar transistors or HBT).
In addition a further impetus in terms of efficiency in relation to SiGe-HBTs has been initiated by the additional incorporation of carbon into the SiGe base layer and/or adjoining silicon regions. SiGe-HBTs with additional carbon incorporation are referred to hereinafter as SiGe:C-HBTs. Those developments firstly related primarily to npn transistors, while in recent times the high-frequency efficiency of pnp transistors could also be drastically improved with the same measures.
General design features, corresponding to the present day state of the art, in respect of complementary bipolar transistors and process steps in a CBiCMOS technology with npn SiGe-HBTs and pnp SiGe-HBTs are published in B. El-Kareh, S. Balster, W. Leitz, P. Steinman, H. Yasuda, M. Corsi, K. Dawoodi, C. Dimecker, P. Foglietti, A. Haesler, P. Menz, M. Ramin, T. Schamagl, M. Schiekofer, M. Schober, U. Schulz, L. Swanson, D. Tatman, M. Waitschull, J. W. Weijtmans and C. Willis: “A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits”, BCTM, pages 211-214, 2003 (hereinafter referred to as El-Kareh et al.). The solution described therein aims at the lowest possible parasitic capacitances and a collector resistance which is as low as possible. Small collector-substrate capacitances are implemented by means of deep trenches filled with insulator material and with a buried silicon oxide layer using SOI technology (“silicon on insulator”). In addition the buried oxide layer in conjunction with the deep trenches ensures electrical insulation of the collectors in relation to the substrate. To keep the collector resistances low El-Kareh et al. use epitaxially buried, highly doped collector layers and special implantation steps for a low-ohmic connection of the buried collector layers, referred to as the “collector sinker”. With that CBiCMOS technology El-Kareh et al. reach limit frequencies fT (transit frequency)/fmax (maximum oscillation frequency) of 19/60 GHz for npn transistors and 19/45 GHz for pnp transistors.
A disadvantage with that process however is that typical modern CMOS technologies include neither epitaxially buried collector layers nor deep insulation trenches nor collector sinkers. The additional process complication and expenditure for the implementation of those structures is in part considerable. As the CMOS transistors are introduced into the epitaxy layer which is deposited over the collector layers buried thereby an additional heat stress in respect of the buried collector layers used by El-Kareh et al. is not to be avoided during the CMOS process. That reduces the profile gradient of the buried collector layers, whereby the efficiency of both types of bipolar transistors but in particular that of the pnp transistors in the high-speed range is adversely affected.
In addition the process described by El-Kareh et al. suffers from the disadvantage that process steps for CMOS and bipolar components are coupled in a way which impedes true modularity of bipolar integration. Thus that arrangement uses a gate electrode in the form of a layer stack which results from two deposition processes and not, as is usual in CMOS processes, a single polycrystalline silicon layer (polysilicon layer). In El-Kareh et al. the gate stack comprises a polysilicon layer and a p-doped polycrystalline SiGe-layer which is produced during deposition of the base of the npn bipolar transistors. That coupling pursues the aim of keeping down the process complication and expenditure and therewith the complexity and costs of the proposed CBiCMOS technology. The disadvantage of that process however is that the interchangeability of process modules, which is usually strived for, is hindered in that way.
As already mentioned hereinbefore the use of an SOI substrate in combination with deep trenches admittedly still affords the advantage of permitting electrical insulation of the bipolar transistors without further technological applications. In addition the collector-substrate capacitance can be kept comparatively low. SOI substrates however have in particular the disadvantage that dissipation of the heat produced in transistor operation is made considerably more difficult, in comparison with standard substrates. That disadvantage causes additional self-heating of the transistors under the operating conditions in the high-speed area and thus leads to a reduction in power potential.
In addition the silicon layers present in El-Kareh et al. on the buried oxide layer of the SOI substrate, in vertical extent, are too powerful to be able to produce optimized MOS transistors, for example so-called fully depleted MOS transistors, on an SOI substrate, without difficulties. Integration of the complementary bipolar transistors with a CMOS technology which was developed for standard substrates requires additional applications just because of the change to an SOI substrate.
Many of the discussed disadvantages of the CBiCMOS process described by El-Kareh et al. and the design features involved therein in respect of the complementary bipolar transistors are avoided in a CBiCMOS process with complementary SiGe:C-HBTs which has been described by B. Heinemann, R. Barth, D. Bolze, J. Drews, P. Formanek, O. Fursenko, M. Glante, K. Glowatzki, A. Gregor, U. Haak, W. Höppner, D. Knoll, R. Kurps, S. Marschmeyer, S. Orlowski, H. Rücker, P. Schley, D. Schmidt, R. Scholz, W. Winkler and Y. Yamamoto: “A complementary BICMOS technology for high-speed npn and pnp SiGe:C-HBTs”, IEDM, pages 117-120, 2003 (hereinafter Heinemann et al.). Thus that CBiCMOS process uses standard substrates and does not require any deep trenches for low collector-substrate capacitances. Integration of the complementary bipolar transistors including collector implantation thereof is effected only after structuring of the standard CMOS gates, which permits truly modular bipolar integration. Heinemann et al., with that CBiCMOS technology, achieve limit frequencies fT/fmax of 180/185 GHz with a breakdown voltage BVCEO of 2V for npn transistors and 80/120 GHz at BVCEO of 2.6V for pnp transistors.
The excellent high-frequency properties of the complementary bipolar transistors of Heinemann et al., produced in a bipolar process implementation which can be modularly integrated without problems into a typical, highly scaled basic CMOS process, result substantially from two features, the use of a novel collector construction and the first use of an SiGe:C-base layer also for pnp transistors. Both features are briefly discussed hereinafter.
The novel collector construction which was described by Heinemann et al. and which is used both for npn and also pnp transistors (with suitable doping inversion) comprises a unitary active region, that is to say a region which is not interrupted by insulation trenches, which is delimited at the outer edge only by shallow silicon oxide-filled trenches. Such shallow trenches, unlike the above-discussed deep trenches, involve depths of markedly less than 1 μm, typically 0.5 μm. Shallow trenches are an ordinary constituent of any modern CMOS technology so that the use thereof in the bipolar module of a BiCMOS or CBiCMOS technology is possible without any additional complication and thus costs. The collector implant (or a succession of collector implants) is introduced into the unitary active region and healed in such a way that the np junction to the p substrate (for the npn transistor) and/or the pn junction to an implanted insulation layer (for the pnp transistor) is no deeper than the bottom of the shallow trenches which outwardly delimit the unitary active region. That initially ensures that low collector-substrate capacitances can be achieved even without the use of a complicated and expensive deep trench insulation.
As the so-called inner base of the transistor and thereover the emitter are formed above the unitary active collector region and then the emitter and the collector are contacted within the plan view onto the unitary collector region, it is also possible to achieve very low collector resistances without using epitaxially buried, highly doped collector layers and special collector sinkers.
The second main feature in the CBiCMOS technology described by Heinemann et al. involves the first use of an SiGe:C-base layer also for the pnp transistor and the introduction of a special n-doping profile during the base deposition process for that type of transistor. That avoids certain disadvantages of the Si/SiGe heterojunction for pnp transistors, see D. V. Singh, J. L. Hoyt, I. F. Gibbons: “Effect of band alignment and density of states on the collector current in p-Si/n-Si1-yCy/p-Si HBTs”, IEDM, pages 749-752, 2000, and improved stability in relation to the diffusion of doping elements is achieved, similarly as in the npn case. That is of benefit to the high-frequency properties of the pnp transistors and in particular their “maintenance” within a CMOS environment with the healing processes which are usually involved there for the source/drain implants which can also act on the base doping profiles of the bipolar transistors in a BiCMOS or CBiCMOS process.
To sum up it can be considered that the CBiCMOS process by Heinemann et al. already has two of the above-mentioned features of an “ideal” integration of bipolar components, in particular complementary bipolar components, in a basic CMOS process, namely the features of “modular bipolar integration” and “high-efficiency bipolar integration”. The third feature that it is striven to achieve, namely “inexpensive bipolar integration” is however still not really achieved in the Heinemann et al. CBiCMOS process. In comparison with the basic CMOS process 10 additional mask steps associated with bipolar integration are required.
The underlying technical problem of the invention is therefore that of providing a complementary bipolar semiconductor device of the kind set forth in the opening part of this specification, which is inexpensive to manufacture and in which both bipolar transistor types have very good properties for high-speed uses.
A further underlying technical problem of the invention is to provide an inexpensive process for the production of a bipolar semiconductor device, which makes it possible to produce both bipolar transistor types with very good properties for high-speed uses.